There is a continuing need for improved flash memory devices. The need for larger storage capacity devices, faster operating devices and/or lower power consuming devices continually drive further scaling of memory devices. However, the scaling of memory devices is constrained by design rules that are technology specific. The design rules specify the minimum feature sizes, spacings and overlaps for the component devices and interconnects, and the maximum misalignment that can occur between two masks. In addition, line width expansion and shrinkage throughout fabrication also strongly affect the design rules.
Referring to FIG. 1, a representation of a memory cell array, according to the conventional art, is shown. The representation illustrates the grid of word lines 110, bit lines 120, drain select gate, source select gate, source line, and corresponding contacts. In the conventional art, the bit line interconnects may include polysilicon plugs (Poly 3), tungsten (W) clad layers, tungsten vias, and M1 interconnects. The source line interconnects may include polysilicon layer buried contacts (Poly 3), Titanium nitride (TiN) barrier layers, and tungsten (W) damascene M1 interconnects. The conventional interconnects require a relatively large number of masks. In addition, the bit line interconnects and source line interconnects are typically fabricated separately. Furthermore, the polysilicon portions of the conventional interconnects are characterized by a relatively high resistance.
In order to continue to scale memory devices, such as NAND flash memories, there is a continuing need to further scale the interconnects. Preferably, the interconnects should be fabricated using as few masks as possible. The resistance of interconnects should also preferably be lower than conventional bit line and source line ground interconnects.